Very large scale integration (VLSI) has been made possible by an ever improving technological ability to create complex electronic circuits. Efficient design of VLSI circuits requires some automatic means for designing the interconnection patterns and for designing the layout of the circuits. In this regard, there are a wide variety of products available in the art to assist in the design of VLSI circuits.
An integral part of all such design tools is a mechanism for evaluating the efficacy of the design. Timing analysis, such as static timing analysis, is one such tool for evaluating the efficacy of the design. In one embodiment of static timing analysis, a full chip or full circuit simulation is required in order to determine timing constraints or requirements for each of a plurality of design blocks. This embodiment typically requires excessive time to implement, which increases the difficulty for design evaluation. For example, a change in one block may affect another block. Accordingly, several revisions of the circuit may be required in order to achieve a properly working circuit. Due, in part, to the excessive time required for evaluation, the time required to design an integrated circuit is long.